ENTERASYS A4H254-8F8T 以太网边缘交换机

ENTERASYS A4H254-8F8T  以太网边缘交换机

ENTERASYS A4H254-8F8T  以太网边缘交换机

在控制系统中，仪器仪表作为其构成元素，它的技术进展是跟随控制系统技术的发展而发展的。目前，控制理论已发展到智能控制的新阶段，自动化仪器仪表的智能化就成为必然了。

仪器仪表的智能化主要归结于微处理器和人工智能技术的发展与应用。

例如运用神经网络、遗传算法、进化计算、混沌控制等智能技术，使仪器仪表实现高速、高效、多功能、高机动灵活等性能。

再如，运用模糊规则的模糊推理技术，对事物的各种模糊关系进行各种类型的模糊决策。

又如，用软件实现信号滤波，如快速傅立叶变换、短时傅立叶变换、小波变换等技术，是简化硬件，提高信噪比，改善传感器动态特性的有效途径。

还如，充分利用人工神经网络技术强有力的自学习、自适应、自组织能力，联想、记忆功能以及对非线性复杂关系的输入、输出间的黑箱映射特性等。

当前，我国智能化领域最薄弱、最需要发展的是仪器、仪表、传感器等基础产业。随着科学技术的飞速发展和自动化程度的不断提高，我国仪器仪表行业也将发生新的变化并获得新的发展。仪器仪表产品的高科技化，特别是智能化，将成为日后仪器仪表科技与产业的发展主流。

系统的软件设计根据硬件结构的总体划分，也可以分为两大部分来描述。整个系统的运行如图2所示，FPGA和DSP各自的程序独立运行，通过中断信号完成数据的实时交互。FPGA向DSP方向的指令是通过FPGA发送一个EDMA请求，DSP通过响应EDMA请求，建立EDMA通道，开始从FIFO中进行预处理后数据的读取，DSP向FPGA传输数据时，通过向FPGA发送一个中断信号，让其从FIFO中把压缩后的图像数据读出来。

整个系统工作流程可以简单描述如下：系统上电后，首先DSP由flash实现自举，并运行引导程序，之后转入EDMA等待状态，FPGA初始化后等待外部图像采集命令，收到图像采集命令后开始进行图像采集，并对采集到的图像进行预处理，预处理后的图像经过FIFO缓冲，在存储一定量的数据之后，FPGA通过半满信号向DSP发送EDMA请求，等待DSP响应，DSP一旦收到来自FPGA的EDMA请求，立即建立EDMA通道，从FIFO中读取数据到L2存储器，存满一帧图像后DSP开始图像压缩，等待一幅图像压缩完成之后，DSP会向FPGA发送中断信号，FPGA在收到中断信号后开始从 FIFO中读取压缩后的图像数据。一帧数据读完后，判断编码信号是否有效，如果有效则按同样的规则对下一帧图像进行压缩，如果无效则通知DSP结束。

ENTERASYS A4H254-8F8T  以太网边缘交换机

In the control system, instruments and meters are its constituent elements, and its technical progress follows the development of control system technology. At present, the control theory has developed to a new stage of intelligent control, and the intelligentization of automatic instruments and meters has become inevitable.

The intellectualization of instruments and meters is mainly attributed to the development and application of microprocessor and artificial intelligence technology.

For example, using intelligent technologies such as neural network, genetic algorithm, evolutionary computation and chaos control, instruments and meters can achieve high speed, high efficiency, multi-function and high flexibility.

Another example is the use of fuzzy reasoning technology of fuzzy rules to make various types of fuzzy decisions on various fuzzy relations of things.

For another example, using software to realize signal filtering, such as fast Fourier transform, short-time Fourier transform and wavelet transform, is an effective way to simplify hardware, improve signal-to-noise ratio and improve sensor dynamic characteristics.

For example, make full use of the powerful self-learning, self-adaptation and self-organization capabilities of artificial neural network technology, the functions of association and memory, and the black-box mapping characteristics between input and output of nonlinear complex relationships.

At present, the basic industries such as instruments, meters and sensors are the weakest and most in need of development in the field of intelligence in China. With the rapid development of science and technology and the continuous improvement of automation, China's instrument industry will also undergo new changes and obtain new development. High-tech instrumentation products, especially intelligence, will become the mainstream of instrumentation technology and industry in the future.

According to the overall division of hardware structure, the software design of the system can also be described in two parts. The operation of the whole system is shown in Figure 2. The programs of FPGA and DSP run independently, and the real-time interaction of data is completed through interrupt signals. The instruction from FPGA to DSP is to send an EDMA request through FPGA. DSP responds to the EDMA request, establishes an EDMA channel, and starts to read the preprocessed data from FIFO. When DSP transmits data to FPGA, it sends an interrupt signal to let it read the compressed image data from FIFO.

The workflow of the whole system can be simply described as follows: after the system is powered on, first, the DSP is bootstrapped by flash, and the boot program is run, and then it turns to the EDMA waiting state. After the FPGA is initialized, it waits for the external image acquisition command, and after receiving the image acquisition command, it starts to acquire the image, and preprocesses the acquired image. The preprocessed image is buffered by FIFO, and after storing a certain amount of data, The FPGA sends an EDMA request to the DSP through a half-full signal, waiting for the DSP to respond. Once the DSP receives the EDMA request from the FPGA, it immediately establishes an EDMA channel, reads data from the FIFO into the L2 memory, and starts image compression after a frame of image is filled. After an image compression is completed, the DSP sends an interrupt signal to the FPGA, and the FPGA starts reading the compressed image data from the FIFO after receiving the interrupt signal. After reading a frame of data, it is judged whether the coded signal is valid. If it is valid, the next frame of image is compressed according to the same rules. If it is invalid, it is notified to DSP to end.

ENTERASYS A4H254-8F8T  以太网边缘交换机