ABB PM866K01 3BSE050198R1 模拟量输入模块

ABB PM866K01 3BSE050198R1  模拟量输入模块

ABB PM866K01 3BSE050198R1  模拟量输入模块

　MB86S02视频图像传感器在FPGA的控制下进行视频图像信息的采集，在收到PC机的采集命令后MB86S02开始视频信号的采集 FPGA作为系统的核心控制单元不仅负责视频图像的采集，而且负责视频图像信息的预处理和系统各单元模块之间的数据交互。针对视频图像数据量大的特点，为了保证系统的实时性要求，系统采用大容量的片外SDRAMR对采集到的视频图像信息进行缓存，SDRAM控制器由FPGA实现，视频图像信息经过 SDRAM缓存后首先要由FPGA对其进行滤波处理，以消除图像信息中的噪声干扰，本系统中采用中值滤波的方式对采集到的视频信息进行处理，滤波后的数据通过FPGA内部FIFO进入DSP进行下一步的压缩处理。DSP上电后首先进行引导程序的自加载，等待FPGA发送请求，在收到FPGA的请求后，DSP建立EDMA通道从FPGA获取视频数据，存满一帧后，开始对视频图像进行JPEG压缩处理，压缩处理后的视频图像信息经过FIFO缓存后，在 FPGA的控制下写入USB接口控制器的数据缓存区，等待PC机的读数请求，USB接口控制器在收到PC机的读数请求后将数据写入PDIUSBD12的端口1，以便PC机下一步读取数据。

ABB PM866K01 3BSE050198R1  模拟量输入模块

MB86S02 video image sensor collects video image information under the control of FPGA. After receiving the acquisition command from PC, MB86S02 starts to collect video signals. As the core control unit of the system, FPGA is not only responsible for the collection of video images, but also for the preprocessing of video image information and the data interaction among all units and modules of the system. In view of the large amount of video image data, in order to ensure the real-time requirements of the system, the system uses a large-capacity off-chip SDRAMMR to cache the collected video image information, and the SDRAM controller is realized by FPGA. After the video image information is cached by SDRAM, it must be filtered by FPGA to eliminate the noise interference in the image information. In this system, the collected video information is processed by median filtering, and the filtered data enters the DSP through the internal FIFO of FPGA for further compression. After the DSP is powered on, it first loads the boot program and waits for the FPGA to send a request. After receiving the request from the FPGA, the DSP establishes an EDMA channel to obtain video data from the FPGA, and after storing a full frame, it starts JPEG compression of the video image. After the compressed video image information is buffered by the FIFO, it is written into the data buffer area of the USB interface controller under the control of the FPGA, waiting for the reading request of the PC. The USB interface controller writes the data into port 1 of PDIUSBD12 after receiving the reading request from the PC, so that the PC can read the data next.

ABB PM866K01 3BSE050198R1  模拟量输入模块

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