SST-1500-YCX-3-1-0 处理来自各种电信号的输入

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1）备件

2）保修期：12个月！

3）包装：原包装与纸箱。

4）交货时间：付款后3天内发货

5）所有货物将在发货前进行测试。

SST-1500-YCX-3-1-0模块化构建模块以高速和高精度处理来自各种电信号的输入，并能为自动操作提供可编程的响应。非常适合步进电机、测量系统、自动化和PLC应用。MLX模块是最通用的KurtUSB模块。它的核心是一个强大的CPU，以惊人的速度和精度处理电信号。由于这种处理能力，来自不同类型传感器的信号可以通过软件进行处理，使MLX可以轻松地配置为与几种不同类型的设备一起工作，包括:LVDT探针、空气-电转换器、温度传感器、涡流传感器，并且可以为独特的应用提供定制软件。通过内部可编程逻辑控制器(PLC),MLX可利用工业标准梯形逻辑进行编程，以响应输入，并可通过离散输出、步进电机、模拟输出或远程DeviceNet设备(未来固件版本)控制复杂的自动化设备。利用USB 2.0通信，可在MLX模块和个人计算机之间进行SST-1500-YCX-3-1-0高速数据传输。MLX对个人计算机的更新速度或数据速率达到每秒40，000次是可能的。

整个系统工作流程可以简单描述如下：系统上电后，首先DSP由flash实现自举，并运行引导程序，之后转入EDMA等待状态，FPGA初始化后等待外部图像采集命令，收到图像采集命令后开始进行图像采集，并对采集到的图像进行预处理，预处理后的图像经过FIFO缓冲，在存储一定量的数据之后，FPGA通过半满信号向DSP发送EDMA请求，等待DSP响应，DSP一旦收到来自FPGA的EDMA请求，立即建立EDMA通道，从FIFO中读取数据到L2存储器，存满一帧图像后DSP开始图像压缩，等待一幅图像压缩完成之后，DSP会向FPGA发送中断信号，FPGA在收到中断信号后开始从FIFO中读取压缩后的图像数据。一帧数据读完后，判断编码信号是否有效，如果有效则按同样的规则对下一帧图像进行压缩，如果无效则通知DSP结束。

SST-1500-YCX-3-1-0 处理来自各种电信号的输入

The SST-1500-YCX-3-1-0 modular building block processes inputs from a variety of electrical signals with high speed and precision, and provides programmable responses for automated operations. Ideal for stepper motors, measurement systems, automation and PLC applications. The MLX module is the most versatile KurtUSB module. At its heart is a powerful CPU that processes electrical signals with incredible speed and precision. Thanks to this processing power, signals from different types of sensors can be processed by software, making the MLX easily configurable to work with several different types of devices, including :LVDT probes, air-electrical converters, temperature sensors, eddy current sensors, and custom software can be provided for unique applications. With an internal programmable logic controller (PLC), the MLX can be programmed with industry-standard ladder logic to respond to inputs and can control complex automation devices via discrete outputs, stepper motors, analog outputs, or remote DeviceNet devices (future firmware versions). Using USB 2.0 communication, SST-1500-YCX-3-1-0 high-speed data transfer is possible between the MLX module and the personal computer. It is possible for MLX to update a personal computer at a rate or data rate of 40,000 times per second.

The whole system workflow can be simply described as follows: After the system is powered on, the DSP is bootstrapped by flash first, and the boot program is run, and then it is transferred to the EDMA waiting state. After initialization, the FPGA waits for the external image acquisition command. After receiving the image acquisition command, the image acquisition begins, and the acquired image is preprocessed. After storing a certain amount of data, FPGA sends EDMA request to DSP through half-full signal, waiting for DSP response. Once DSP receives EDMA request from FPGA, it immediately establishes EDMA channel, reads data from FIFO to L2 memory, and starts image compression after storing one frame of image. After an image compression is completed, the DSP sends an interrupt signal to the FPGA, and the FPGA begins to read the compressed image data from the FIFO after receiving the interrupt signal. After reading a frame of data, the encoded signal is judged whether it is valid. If it is valid, the next frame image is compressed according to the same rules. If it is invalid, the DSP is notified to end.

SST-1500-YCX-3-1-0 处理来自各种电信号的输入

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