SYHNC100-NIB-23 W-24-P-D-E23-A012 控制器

SYHNC100-NIB-23 W-24-P-D-E23-A012 控制器

SYHNC100-NIB-23 W-24-P-D-E23-A012 控制器

系统的软件设计根据硬件结构的总体划分，也可以分为两大部分来描述。整个系统的运行如图2所示，FPGA和DSP各自的程序独立运行，通过中断信号完成数据的实时交互。FPGA向DSP方向的指令是通过FPGA发送一个EDMA请求，DSP通过响应EDMA请求，建立EDMA通道，开始从FIFO中进行预处理后数据的读取，DSP向FPGA传输数据时，通过向FPGA发送一个中断信号，让其从FIFO中把压缩后的图像数据读出来。

整个系统工作流程可以简单描述如下：系统上电后，首先DSP由flash实现自举，并运行引导程序，之后转入EDMA等待状态，FPGA初始化后等待外部图像采集命令，收到图像采集命令后开始进行图像采集，并对采集到的图像进行预处理，预处理后的图像经过FIFO缓冲，在存储一定量的数据之后，FPGA通过半满信号向DSP发送EDMA请求，等待DSP响应，DSP一旦收到来自FPGA的EDMA请求，立即建立EDMA通道，从FIFO中读取数据到L2存储器，存满一帧图像后DSP开始图像压缩，等待一幅图像压缩完成之后，DSP会向FPGA发送中断信号，FPGA在收到中断信号后开始从 FIFO中读取压缩后的图像数据。一帧数据读完后，判断编码信号是否有效，如果有效则按同样的规则对下一帧图像进行压缩，如果无效则通知DSP结束。

SYHNC100-NIB-23 W-24-P-D-E23-A012 控制器

According to the overall division of hardware structure, the software design of the system can also be described in two parts. The operation of the whole system is shown in Figure 2. The programs of FPGA and DSP run independently, and the real-time interaction of data is completed through interrupt signals. The instruction from FPGA to DSP is to send an EDMA request through FPGA. DSP responds to the EDMA request, establishes an EDMA channel, and starts to read the preprocessed data from FIFO. When DSP transmits data to FPGA, it sends an interrupt signal to let it read the compressed image data from FIFO.

The workflow of the whole system can be simply described as follows: after the system is powered on, first, the DSP is bootstrapped by flash, and the boot program is run, and then it turns to the EDMA waiting state. After the FPGA is initialized, it waits for the external image acquisition command, and after receiving the image acquisition command, it starts to acquire the image, and preprocesses the acquired image. The preprocessed image is buffered by FIFO, and after storing a certain amount of data, The FPGA sends an EDMA request to the DSP through a half-full signal, waiting for the DSP to respond. Once the DSP receives the EDMA request from the FPGA, it immediately establishes an EDMA channel, reads data from the FIFO into the L2 memory, and starts image compression after a frame of image is filled. After an image compression is completed, the DSP sends an interrupt signal to the FPGA, and the FPGA starts reading the compressed image data from the FIFO after receiving the interrupt signal. After reading a frame of data, it is judged whether the coded signal is valid. If it is valid, the next frame of image is compressed according to the same rules. If it is invalid, it is notified to DSP to end.

SYHNC100-NIB-23 W-24-P-D-E23-A012 控制器